Field
Embodiments of the present disclosure generally relate to methods and apparatus for forming a semiconductor device. More specifically, embodiments described herein relate to a method for controlling channel height in a transistor.
Description of the Related Art
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 7 nm or smaller dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. Recently, complementary metal oxide semiconductor (CMOS) devices having fin field-effect transistors (FinFETs) or tunnel field-effect transistors (TFETs) have been widely used in many logic and other applications and are integrated into various different types of semiconductor devices.
Group III-V semiconductors, such as indium (In), gallium (Ga), and arsenic (As), may serve as a channel, or fin, material for sub-7 nanometer (nm) CMOS devices due to the low contact resistance, superior electron mobility and lower operation voltage. During the formation of the channel region, a portion of a group III-V semiconductor material may be removed to form a recessed depth. Conventional material removal processes, such as thermal, wet or dry etch, have certain drawbacks. High temperature thermal removal process is not suitable because of As diffusion and In/Ga segregation at high temperatures, as well as pits formation on the surface. Wet etch is not suitable because wet etch is typically performed ex-situ and is not good to control group III-V semiconductors recess depth with different feature sizes. High power RF plasma etch can damage the surface and causing residual oxygen implanting, as well as large etch depth loading.
Therefore, there is a need for an improved methods for forming group III-V semiconductor channels.